1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method for forming silicided electrodes of MISFETs (Metal Insulator Semiconductor Field Effect Transistors).
2. Background Art
In recent years, the size shrinking of semiconductor devices has been advanced. As a result, it is demanded to shrink dimensions in a direction horizontal to a semiconductor substrate plane such as gate dimensions of transistors, the element isolating insulation film width, and the interconnection width. In addition, it is demanded to shrink dimensions in a direction perpendicular to the semiconductor substrate plane such as the height of a gate electrode and the junction depth of a source-drain diffusion layer as well.
On the other hand, it is demanded to, for example, form a low-resistance silicide film on the gate electrode and the source-drain diffusion layer to reduce parasitic resistance in these regions.
Therefore, the so-called salicide (self-aligned silicide) process for forming a low-resistance silicide film on the gate electrode or on the surface of the source-drain diffusion layer is applied (see, for example, Japanese Patent Laid-Open No. 2005-19705 and Japanese Patent Laid-Open No. 11-251591).